The present disclosure relates to integrated circuit fabrication, and more specifically, to a strain retention semiconductor member for a compressive channel silicon germanium (cSiGe) layer for a p-type field effect transistor (pFET), and a related method and IC structure.
In integrated circuits, field effect transistors (FETs) are used widely. The terminals of the FETs are designated source (S), drain (D) and gate (G). FETs rely on an electric field to control the shape and hence the conductivity of a “channel” in a semiconductor material between the source and drain regions. P-type field effect transistors (pFETs) are formed with p-type dopants in the semiconductor material in the source/drain region which generate a free hole (by “accepting” electron from semiconductor atom and “releasing” hole at the same time). Boron (B) is the most common acceptor in silicon technology, but alternatives include indium and gallium.
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (pFET) drive currents). In order to boost the performance of pFETs formed on fully depleted semiconductor-on-insulator (FDSOI) substrates, a compressive channel silicon germanium (cSiGe) layer is used to form the pFET. More specifically, a relatively thin compressive cSiGe layer is formed by, for example, germanium condensation, on the FDSOI substrate before shallow trench isolation (STI) formation in the FDSOI substrate. The gate of the PFET is then formed on the compressive cSiGe layer followed by p-type dopant epitaxy to form raised source and drain regions adjacent the gate. The gate is formed by conventional photolithographic and/or sidewall transfer techniques. The terms “epitaxial growth” and “epitaxially formed and/or grown” mean the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial growth process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface.
There are a number of challenges presented by the relatively thin compressive cSiGe layer, which must be addressed as current device miniaturization continues thinning the compressive cSiGe layer, e.g., beyond 6 nm. One of the challenges of using compressive cSiGe is maintaining the compressive strain in the relatively thin compressive cSiGe layer, which can have a thickness of, for example, approximately 6-7 nanometers (nm). In particular, the compressive strain is locked to the FDSOI substrate lattice during formation of the compressive cSiGe layer. Formation of trench isolations in the FDSOI substrate, which is required to insulate different regions/devices formed on the substrate, requires formation of trenches in the FDSOI substrate. The trenches and related thermal activity relaxes or releases the compressive strain in the compressive cSiGe layer, impeding the performance improvements for the pFETs. Another challenge is growing a p-type doped epitaxial layer (e.g., using boron) on the relatively thin compressive cSiGe layer for the raised source/drain regions. In particular, when the compressive cSiGe layer is relatively thin, e.g., approximately 6 nm or less, the epitaxial growth for the raised source/drain regions commonly results in undesirable agglomeration of the semiconductor material. It is therefore difficult to obtain a uniform dopant concentration in the source/drain regions.